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The present invention relates to the formation of integrated circuits on semiconductor wafers. More particularly, embodiments of the invention relate to a method for forming high aspect ratio contacts to a silicon substrate through an overlying borophosphosilicate glass or similar silicon oxide layer.
Borophosphosilicate glass (hereinafter xe2x80x9cBPSGxe2x80x9d) has found wide use in the semiconductor industry as a separation layer between the polysilicon gate/interconnect layer and the first metal layer of MOS transistors. Such a separation layer is often referred to as premetal dielectric (PMD) layer because it is deposited before any of the metal layers in a multilevel metal structure and is used to electrically isolate portions of the first deposited metal layer from the semiconductor substrate. BPSG films are commonly used as PMD layers because of their low dielectric constant, low stress, good adhesion properties and relatively low reflow temperature. Standard BPSG films are formed by introducing a phosphorus containing source and a boron containing source into a processing chamber along with the silicon and oxygen containing sources normally required to form a silicon oxide layer.
When used as a PMD layer, a BPGS film is deposited over a lower level polysilicon gate/interconnect layer that usually contains raised or stepped surfaces. The initially deposited film generally conforms to the topography of the poly layer and is typically planarized or flattened before an overlying metal layer is deposited. A standard reflow process, in which the oxide film is heated to a temperature at which it flows, may be employed to planarize the film. Alternatively, the layer may be partially reflowed and then subject to a chemical mechanical polishing (CMP) or etching technique.
As is known in the art, incorporating more phosphorus and boron into a BPSG typically results in better gapfill characteristics for a given reflow temperature. This effect must be balanced, however, with other concerns such as density of the BPSG layer. Higher dopant levels and lower reflow temperatures are also associated with a decrease in the density of the BPSG layer. Such a decreased density may, in turn, result in overetching during the formation of a contact structure in the layer.
FIGS. 1A through 1C show one example of an integrated circuit that is vulnerable to such an over etching problem. FIG. 1A is a top view of a portion of a contact structure formed through a BPSG layer and FIG. 1B is a cross sectional view of the contact structure along line A1-A2 shown in FIG. 1A. As shown in FIGS. 1A and 1B, adjacent polycide structures 12, 14 and 16 have been formed over a silicon substrate 10. Structures 12, 14 and 16 each include a first polysilicon layer 18 and an overlying tungsten silicide layer 20. A self-aligned silicon nitride layer 22 is deposited over the gate and a BPSG layer 24 is formed over the entire substrate. BPSG layer 24 has been reflowed and polished to a flat upper surface 26, and contact holes 28 that provide contact to the silicon substrate from an upper metalization layer have been etched between structures 12 and 14 and between structures 14 and 16 as well as in other places of the substrate that are not shown in either FIG. 1A or 1B. Also shown in FIGS. 1A and 1B are N-well 30, P-well 32, shallow trench isolation region 34 and source and drain regions 36. It should be noted that FIGS. 1A and 1B have not been drawn to scale and that certain features have been exaggerated in size relative to others for ease of illustration.
FIG. 1C is an enlarged view of area 38 shown in FIG. 1A. While FIG. 1C is drawn closer in scale than either of FIGS. 1A and 1B in order to better illustrate the problems faced in the formation of contacts 28, it is still not drawn to the correct scale. As shown in FIG. 1C, contact holes 28 are formed through the middle of high aspect ratio gaps 40 that exist between adjacent gate structures and are filled with BPSG material. In some applications, high aspect ratio (HAR) gaps are characterized by a top width 42 of between 0.05 and 0.09 microns, a bottom width 44 of between 0.02 and 0.05 microns and a sidewall angle 46 of between 85-89 degrees. With a gaps"" aspect ratio defined as the ratio of it""s height to the width at the center of the gap, the aspect ratio for such HAR gaps is typically between 6:1 to 10:1 in 0.13 and 0.10 micron feature size technology. As can be appreciated, semiconductor manufacturers are pushing current technology to the limit in order to fill such a high aspect ratio gap with BPSG layer 24 in a void free manner so that layer 24 also has other characteristics, e.g., appropriate dielectric constant, adhesion and density, necessary to produce working integrated circuits.
Ideally, contact holes 28 are characterized by smooth nearly vertical lines 40 throughout the entire contact area. After the contact holes are etched they are typically filled with a multilayer metal plug such as a titanium/titanium nitride/tungsten scheme as is known in the art.
In some applications contact holes 28 are subject to a contact clean step in order to remove oxidation and/or residue remaining from the contact etch step at the silicon contact surface prior to forming metallization within the holes. Such a contact clean step may be done by wet clean process (e.g., using a solution of ammonium hydroxide and hydrogen peroxide diluted in water), by plasma clean process or by using other techniques, such as ultrasonic or megasonic cleaning. Regardless of what technology is used, care must be taken during the clean step in order to ensure that the contact opening is not overetched thereby undesirably widening the contact holes.
As previously mentioned, the doping concentration of the BPSG layer and reflow temperature must be balanced against other concerns. Too high of a dopant concentration and/or too low of a reflow temperature will result in a less dense BPSG layer that has a high etch rate. In such a case, the BPSG layer is more susceptible to the overetching just described during the contact clean process.
Accordingly, as can be appreciated from the above, it is desirable to develop techniques that reduce the likelihood of overetching contact holes during the contact clean process.
Embodiments of the present invention pertain to methods of reducing the likelihood that contact holes will be overetched during a contact clean process. According to one embodiment, after etching the contact holes but prior to removing residue and/or oxidation within the contact area of the holes via a contact clean process, the holes are subject to a nitrogen plasma that forms a thin nitrided layer on the inner surface of the etched hole. This nitrided layer has a higher etch selectivity to the contacts clean etch process than does the BPSG layer and thus helps prevent overetching of the contact opening during the preclean process.
In another embodiment, a thin layer of silicon nitride is deposited within the contact hole using an atomic layer deposition (ALD) process. In still other embodiments, a thin silicon nitride layer is deposited using chemical vapor deposition (CVD) techniques. In one embodiment, a plasma of silane (SiH4) and either or both ammonia (NH3) and molecular nitrogen (N2) is employed to form the silicon nitride layer. The substrate is heated to a temperature between 200-400xc2x0 C. during deposition of the layer. This CVD process may employ standard capacitively coupled electrodes, high density plasma techniques or remote plasma techniques.
These and other embodiments of the invention along with many of its advantages and features are described in more detail in conjunction with the text below and attached figures.